1) Field of the Invention
The present invention relates to a technology for designing a large-scale-integrated (LSI) chip layout.
2) Description of the Related Art
Conventionally, two-stage wiring has been performed in a layout of the LSI chip. In the two-stage wiring, the LSI chip is divided into a plurality of lattices by using a net of a user from a net list, an ideal wiring routine is searched by a computer aided design (CAD), and global wiring is performed. Then, detailed wiring inside each of the lattices is performed. The technologies used for the two-stage wiring are disclosed in, for example, Japanese Patent Application Laid-Open Publication No. H1-207947, Japanese Patent Application Laid-Open Publication No. H5-160375, Japanese Patent Application Laid-Open Publication No. H5-181936, and Japanese Patent Application Laid-Open Publication No. H7-86404.
Recently, to reduce man-hours required for timing closure work and designing time, a structured application specific integrated circuit (ASIC) that is designed in advance, and in which a SCAN circuit and a built-in self-test (BISt) circuit are embedded, has been developed. In this structured ASIC, from among wiring levels are shared and the rest of the wiring layers are customized-wiring layers that can be customized depending on specifications of a user.
However, in the conventional technologies disclosed in Japanese Patent Application Laid-Open Publication No. H1-207947, Japanese Patent Application Laid-Open Publication No. H5-160375, Japanese Patent Application Laid-Open Publication No. H5-181936, and Japanese Patent Application Laid-Open Publication No. H7-86404, when the global wiring in each lattice of the LSI chip passes through a cell that is arranged in the lattice, the detailed wiring is performed in such a manner that the cell in the lattice in one of the layers is by-passed or by by-passing through other wiring layer.
Therefore, in the structured ASIC, if the layout designing is carried out by the detailed wiring, a wiring pattern of the customized wiring layer may differ in each of the LSI chip. Therefore, a manufacturing process of the LSI chip becomes complicated and the time required for manufacturing increases. As a result, there is an increase in the manufacturing cost.